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Perftrends is currently hiring and looking for
chip design Engineers for its facility in Chennai, India. The positions offered
are:
Project Leader/Managers (Code PT-001)
Hands on Chip design and verification experience
of 8 years or more. Delivered successful silicon of 500K or higher gate count.
Excellent leadership qualities.
Senior Engineers (Code PT-002)
Chip design and verification experience of 5 years or more.
Design Engineers (Code PT-003)
Chip design and verification experience of 2 years or more.
All of the above positions require BS/BE/B.Tech or
MS/ME/M.Tech degree in EEC. For all positions work experience is must in most of
the following technologies: RISC CPUs, DDR SDRAM, PCI-X, PCI-Express, Network
protocols etc. Also candidates must have experience in designing RTL with
Verilog/VHDL, writing verification models in C/C++, System C
etc. Experience in coverage based verification methodology would be
considered plus.
Apply by e-mail to hrd@perftrends.com. Please mention the code in the e-mail subject.
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